Communication systems and the like use a variety of clocks and frequencies to modulate information, transmit information, decode information and the like. The operation and alignment of clocks can be required for proper operation.
For example, in processor based systems, a partition of the system works on a fixed frequency while another partition of the system operates using dynamic frequency scaling, also referred to as a variable clock, based on operation/performance of the system.
Due to high frequency scaling between the variable clock and the fixed clock, these clocks are generally not able to be generated from a single phase locked loop (PLL). As a result, the variable clock and the fixed clock are typically generated from separate PLLs.
What is needed are techniques to dynamically align clocks for communication systems and/or processor based systems.